To verify the correct operation of manufactured circuits, it is desirable for the circuits not only to have correct functional behavior, but also to operate correctly at a certain clock frequency (e.g., the operational clock frequency). As logic circuits operate at higher frequencies and as feature sizes shrink, manufactured circuits become more vulnerable to timing-related defects.
Delay fault testing has therefore become a desirable part of integrated circuit testing and can be used to help achieve high test quality. Delay-related defects typically originate from process variations and random defects. Process variations are ordinarily caused by physical parameter variations during the manufacturing process and usually cannot be completely eliminated. Tightly controlling the process variations and adding extra delay margins during the design phase are two common methods to help tolerate process variations. Random delay defects, caused for example by resistive shorts and resistive vias, introduce additional delays and may also cause circuits to malfunction during normal operation.
Various fault models have been proposed to target delay defects. The transition fault model, for instance, considers a gross delay at every gate terminal in the circuit and assumes that the additional delay at the fault site is large enough to cause a logic failure. See, e.g., J. A. Waicukauski, E. Lindbloom, B. K. Rosen, and V. S. Iyengar, “Transition Fault Simulation,” IEEE Design & Test of Computer, pp. 32-38 (April 1987). Due to the limited fault population with the transition fault model, the model has been widely used in industry. However, transition fault test generation generally ignores the actual delays through the fault activation and propagation paths, and is more likely to detect a fault through a shorter path. As a result, the generated test set may not be capable of detecting small delay defects.
To improve the quality of delay defect test sets such that small delay defects can be detected, it is desirable to integrate timing information into one or more stages of the test generation process.